Omar SobhandClaude Opus 4.7
7b23f61632
Hand-authored skill catalog anchored to real 2026-07 versions:
- Rust 1.97.1 (stable), edition 2024
- React 19.2.7, Server Components + Actions
- TailwindCSS 4.3.3 (CSS-first config, Oxide engine)
- three.js r185 (WebGPURenderer stable, BatchedMesh matured)
- React Native 0.86 / Expo SDK 54+ (New Architecture default)
- cargo-nextest 0.9.140, gitleaks 8.20+, cargo-audit 0.21+
- Postgres 17 (18 in beta, don't rely on)
- CUDA Blackwell, Metal Apple7+, ROCm CDNA3
Ships 15 skills across the categories:
foundation/ workspace-repo-commit-protocol
small-focused-commits
tdd-red-green-refactor
code-review-checklist
int-xx-marker-protocol
decompose-int-items
rust/ write-rust-current-edition
rust-error-handling
cargo-test-driven-development
rust-async-tokio-idioms
backend/ postgres-migrations-forward-only
postgres-index-selection
api-pagination-day-1
frontend/ react-19-server-components
tailwind-v4-idioms
component-4-state-model
mobile/ expo-managed-vs-bare
rn-flashlist-perf
gpu/ gpu-coalescing-and-occupancy
roofline-model
threejs/ threejs-perf-and-teardown
security/ cargo-audit-workflow
secret-scanning-gitleaks
skills_loader.rs walks skills/**/*.md, parses YAML frontmatter
(name, description, when_to_use, tags), upserts via
skills_catalog::upsert_builtin. Idempotent per boot — bumps version
+ appends skill_versions row ONLY when body changes. Deterministic
sha256-derived ids so builtins are stable across boots.
Dockerfile copies skills/ to /etc/clawmates/skills. Server boot
task spawns loader alongside team_template_loader.
Follow-ups (Slice 3.5c continuation, future PRs):
- 20-30 more skills (duckdb, shadcn composition, a11y, WebGPU
migration, metal frame capture, rocprof, deep gitea forge
integration, semgrep rulepacks)
- Bind skills to team template roles (add [role.skills] refs to
templates/teams/*.toml + wire template_role_skills population
in team_template_loader)
Co-Authored-By: Claude Opus 4.7 <[email protected]>
67 lines
3.0 KiB
Markdown
67 lines
3.0 KiB
Markdown
---
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name: gpu-coalescing-and-occupancy
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description: The two knobs that dominate GPU perf — memory coalescing + occupancy targets across CUDA (Blackwell), Metal (Apple 7+), ROCm (RDNA3/CDNA3).
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when_to_use: You're a kernel_author or bench_engineer profiling a GPU kernel. GPU team pins.
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tags: [gpu, cuda, metal, rocm, performance]
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---
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# Coalescing + occupancy
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Two dominant knobs on ANY modern GPU. Get them right first; then worry about smaller wins.
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## Coalescing
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**Rule**: consecutive threads in a warp/wavefront should read consecutive 32/64/128-bit words.
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- **CUDA (Blackwell, SM_100+)** — warp = 32 threads. Threads 0..31 accessing `arr[tid]` = 1 memory transaction. `arr[tid * stride]` for stride > 1 = multiple transactions. Violation cost: 4×–32× slowdown depending on stride.
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- **Metal (Apple 7+, i.e., A17 / M3+)** — SIMD-group = 32 threads, same principle. `metal::simd_shuffle` for cross-lane comms without shared memory.
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- **ROCm (RDNA3, CDNA3)** — wavefront = 32 (RDNA) or 64 (CDNA). Same rule; note the 64-wide wavefronts on CDNA change your indexing math.
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Prove coalescing in a comment on the kernel:
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```cpp
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// Coalesced: thread tid reads global[tid], stride-1.
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// Warp-level transaction: 1× 128-byte load per warp.
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float x = global_in[gid];
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```
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## Occupancy
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Rough targets:
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- **Memory-bound kernel**: aim for **≥ 50% occupancy** to hide DRAM latency.
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- **Compute-bound kernel with high ILP**: 25%–50% is often fine; more threads compete for registers + shared memory.
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Occupancy is bounded by whichever hits first:
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- Registers per thread × threads per block ≤ register file per SM.
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- Shared / threadgroup memory per block ≤ per-SM budget.
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- Threads per block ≤ max (typically 1024).
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Tools:
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- **Nsight Compute** (CUDA): `--section=Occupancy` prints the bottleneck.
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- **Xcode GPU Frame Capture** (Metal): occupancy chart in the performance report.
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- **rocprof** (ROCm): `--stats` for kernel occupancy.
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## Memory hierarchy strategy
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Order-of-magnitude comparison — always prefer the fastest tier your data footprint allows:
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| Tier | CUDA name | Latency | Notes |
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|---|---|---|---|
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| Register | reg | ~1 cycle | Per-thread; too many spills to L1 |
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| Shared | shared / threadgroup / LDS | ~30 cycles | Per-block. CUDA: 48–100 KB. Metal: 32 KB (Apple7+). ROCm: 64 KB LDS |
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| L1 / texture | L1 tex | ~200 cycles | Cache; some HW has separate paths |
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| L2 | L2 | ~500 cycles | Shared across SMs |
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| Global | DRAM / HBM | 400–800 cycles | Coalescing matters MOST here |
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## Divergence
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- Warp-uniform control flow keeps all lanes active.
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- `if (tid % 2)` splits the warp — half the lanes idle per branch.
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- On CUDA Volta+ (7.0+), Independent Thread Scheduling makes divergence CORRECT under all conditions but doesn't make it FAST.
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## The one bottleneck rule
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After profiling, report ONE bottleneck to attack next. Reporting five doesn't help — you'll fix one and re-profile anyway.
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Format:
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> `KERNEL foo achieves 340 GB/s of 3.35 TB/s HBM = 10% BW-bound. Occupancy 62%. Bottleneck: stride-2 loads from arr — refactor tile shape to coalesce.`
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