14 Commits

Include renames

Author	SHA1	Message	Date
Omar SobhandClaude Opus 5	796b8487ad	rtx-backend-cuda: native index_select / index_add — HetGAT training 2.5x, inference 4.3x ... The Backend trait's index_select and index_add have default bodies that round-trip through host memory. That is correct everywhere and was the only implementation CUDA had. Graph message passing is made of these two ops, so dg-gnn's HetGAT paid a device->host->device copy per layer per pass and the RTX 5060 Ti sat at ~10% utilisation during training. Design follows rtx-backend-metal's ops::index: gather is one thread per output element; scatter-add walks the CSR of the adjoint selection matrix S^T, built host-side by counting sort, so it needs NO atomics and is deterministic with duplicate indices — the training loss is bit-identical to the host reference. Device index buffers are cached per thread keyed by the exact index list, so a static graph topology uploads once. Two small NVRTC kernels; no cuSPARSE. Measured on dg-gnn, Harris 42,955 links, v8 recipe, RTX 5060 Ti: training batch 8 9,042 -> 3,562 ms/step (2.5x) inference single p50 55.4 -> 12.9 ms (4.3x) inference batch 8 257 -> 20 ms/scen (13x; batching helps again) GPU utilisation median 10% -> 21%, p90 17% -> 43% Tests: gather with repeats, scatter-add with duplicates and untouched rows, the adjoint identity <S x, y> == <x, S^T y> (what autograd relies on), a hub-heavy pattern against the host reference, and the range-check panic. rtx-backend-cuda --features cuda: 60 + 16 passed, 0 failed. Co-Authored-By: Claude Opus 5 <[email protected]>	2026-09-11 23:09:01 -05:00
osobhandClaude Sonnet 5	4aaa36a57a	style: cargo fmt --workspace (whitespace/wrapping only, no semantic change) ... Whole-workspace rustfmt pass picked up while iterating on Mamba GPU backward work. Verified formatting-only via diff sampling; no logic changed. Co-Authored-By: Claude Sonnet 5 <[email protected]>	2026-08-10 07:09:36 -07:00
osobhandClaude Fable 5	5f32165184	chore(sweep): delete 43 orphaned source files; document SYCL/demo/duplication status ... Deletions (all verified unreferenced by any mod/include/path declaration; git history preserves them): - rtx-transformers: entire orphaned curriculum/ split (mod.rs holds the real inline implementation), non-_simple graph variants, superseded simmim/jepa_integration files, layers/{sliding_window_attention, positional_encoding,ssm_state_cache_original}, lib_full/lib_minimal/ error_full/error_minimal, orphaned MoE impls (moe_layer, moe_integration). - rtx-distributed/parallel_old.rs; rtx-flash-attention/{core_full, lib_full}.rs; rtx-compress legacy_distillation + structured_pruner. - rtx-tensor/tensor_core.rs; rtx-runtime/{cuda_kernel_ops, cuda_backend_mock}.rs; rtx-memory/{gpu_pool_manager,allocator, pool_type}.rs; rtx-losses/{lib_minimal,lib_full}.rs. Docs honesty: - rtx-backend-sycl marked EXPERIMENTAL SKELETON in crate docs and CLAUDE.md backend table (all ops return NotImplemented). - docs/consolidation.md records canonical MoE (layers/mixture_of_experts) and flash-attention (rtx-flash-attention crate) implementations plus remaining duplicates to consolidate. - CLAUDE.md: meta-crate GPU features noted; simulation-only demos named; serving/streaming mock removal noted. Verified: cargo check --workspace clean (rtx-onnx-codegen pre-broken at HEAD, unrelated); lib tests pass for all touched crates (rtx-runtime's 4 failures pre-exist at HEAD). Co-Authored-By: Claude Fable 5 <[email protected]>	2026-07-09 19:32:21 -07:00
osobhandClaude Opus 4.8	e8a2036db4	fix(ci,rtx-tensor): resolve clippy --all-features intel-mkl conflict; gate MKL to x86_64-linux ... clippy --all-features enabled both rtx-tensor/mkl (intel-mkl-src mkl-static-lp64-seq) and rtx-csm/candle mkl (mkl-static-lp64-iomp) -> two conflicting intel-mkl-src link configs -> E0428 'MKL_CONFIG defined multiple times'. - clippy: drop --all-features (lint default features; --all-features is unsound for a multi-platform, mutually-exclusive-backend workspace). - rtx-tensor: gate intel-mkl-src to cfg(all(target_os=linux, target_arch=x86_64)) so mkl is never pulled on macOS/arm. Co-Authored-By: Claude Opus 4.8 <[email protected]>	2026-06-27 08:12:27 -07:00
Claude CodeandClaude Opus 4.8	a25f24494c	feat(rtx-tensor): genericize GenericTensor over B::FloatElem (f64-capable) ... Phase 2 of the rustytorch f32→f64 plan. All 6 `impl<B: Backend<FloatElem = f32>>` blocks on GenericTensor relaxed to `impl<B: Backend>`, with concrete f32 → B::FloatElem (full/from_slice/to_vec/add_scalar/mul_scalar/pow/clamp/leaky_relu/ elu/layer_norm/rms_norm). The genericization was fully clean — every Backend trait scalar param was already Self::FloatElem, so no methods had to stay f32-gated. GenericTensor now works with CpuBackendF64 as well as CpuBackend. Backward-compat holds via B::FloatElem = f32 for CpuBackend: to_vec() still returns Vec<f32>, from_slice still takes &[f32]. Validated: 706 rtx-tensor tests pass (704 f32 + 2 new f64); the f64 test proves 1+2^-30 survives through from_slice/matmul/to_vec (f32 rounds to 1.0). rtx-nn builds; **QPUDIDP's qpu-didp-surrogate (external, ~125 f32 sites) still compiles**. clippy clean. Co-Authored-By: Claude Opus 4.8 (1M context) <[email protected]>	2026-06-26 22:28:26 -07:00
Omar SobhandClaude Sonnet 4.6	082a50e3a0	feat(perf): GPU perf batch 1 — wire GPU execution paths for FP8, FA3, CUDA Graphs, SnapKV ... FP8 GPU FFI (rtx-tensor) - `fp8_cast.rs`: replaced `not_implemented` stubs with real cudarc 0.18.2 PTX launches; `cast_bf16_to_fp8_e4m3` and `cast_fp8_e4m3_to_bf16` now dispatch to NVCC-compiled `fp8_cast.ptx` via `LazyLock` module cache, matching the `inplace_ops` pattern - `build.rs`: `create_dummy_ptx` now emits `fp8_cast.ptx` alongside `element_wise.ptx` so `include_str!` resolves cleanly when NVCC is absent FlashAttention-3 typed kernel launch (rtx-flash-attention) - `flash_v3_forward.rs`: `forward()` now takes typed `CudaSlice<bf16>` Q/K/V/O + `CudaSlice<f32>` LSE buffer; dispatches via `stream.launch_builder` with block_dim=(128,1,1), grid_dim=(ceil(seq_len/64), batch*heads, 1), shared_mem_bytes=0 (PTX metadata-resolved) - `simple.rs`: added `has_flash_v3()` + `flash_attention_v3_forward_raw()` dispatch - `Cargo.toml`: `half` added as optional cuda-gated dependency CUDA Graphs stream threading (rtx-transformers) - `training_loop.rs`: added `cuda_stream: Option<CudaStreamHandle>` field; `set_cuda_backend()` now creates a non-default capture stream; capture step calls real `begin_capture(stream)` + `end_capture(stream)`; added `set_cuda_stream()` override; replay unchanged (no stream needed) SnapKV + prefix cache BatchScheduler wiring (rtx-inference) - `scheduler.rs`: added `prefix_hit_pages: Option<Vec<PageId>>` + `evicted_positions: Vec<usize>` to `SchedulerRequest`; `BatchScheduler` gains `kv_cache` + `snapkv_eviction` fields; `submit_request` does non-blocking `try_lock` prefix lookup; added `notify_prefill_complete` (registers prefix + runs `select_evict_positions`), `set_kv_cache`, `set_snapkv_eviction`, `get_evicted_positions`, `get_prefix_hit_pages` — +5 new integration tests Test results: 22 + 42 + 75 + 102 = 241 tests, 0 failures Co-Authored-By: Claude Sonnet 4.6 <[email protected]>	2026-06-26 20:39:58 +00:00
Omar SobhandClaude Sonnet 4.6	1eb89c5b2b	feat(perf): GPU perf batch 1 — FP8, FA3 Blackwell, CUDA Graphs, SnapKV, prefix cache ... Item 1 — CUDA Graphs wiring (rtx-transformers) - Added `enable_cuda_graphs: bool` (default false) + `cuda_graph_warmup_iters: usize` (default 3) to `TrainingConfig` - Wired 3-phase state machine into `training_loop.rs` (warmup → capture → replay) gated on `#[cfg(feature = "cuda")]`; stream plumbing stubbed with TODO pending `CudaStreamHandle` threading Item 2 — FP8 E4M3/E5M2 training infrastructure (rtx-tensor, rtx-transformers) - `fp8_cast.cu`: dual-path CUDA kernels — SM_89+ uses `<cuda_fp8.h>` native `__nv_cvt_*` intrinsics; older SM uses software bit-manipulation fallback - `fp8_cast.rs`: host-side CPU casting + `#[cfg(feature = "cuda")]` GPU stubs - `fp8_gemm.rs`: bit-accurate E4M3 decoder/encoder, BF16 round-trip utils, CPU reference matmul with cuBLASLt GPU path documented inline; 12 unit tests - `training_config.rs`: `fp8_training: bool`, `fp8_e4m3_forward: bool` - `linear.rs` (modular): `fp8_mode: bool` field + forward dispatch stub - build.rs: registers `fp8_cast.cu` alongside existing `element_wise.cu` - 22 FP8 unit tests — all pass Item 3 — FlashAttention-3 Blackwell (WGMMA + TMA + warp specialization) - `flash_attention_v3_forward.cu`: SM_90+ warp-specialised producer/consumer kernel (producer TMA-loads K/V tiles, consumers run WMMA as portable WGMMA proxy); SM_89+ FP8 header path; SM<90 standard FA2-style WMMA fallback - `flash_v3_forward.rs`: NVRTC wrapper (`compile_ptx` via `include_str!`), `FlashV3ForwardKernel::new/is_supported/forward`; 6 unit tests - `backend_selector.rs`: `SdpaBackend::FlashAttentionV3`, `for_compute_capability`, `supports_flash_v3` (major >= 9), FA3 scoring (0.98/0.90/0.70), 2× speedup estimate - `kernels/simple.rs`: `v3_kernel: Option<FlashV3ForwardKernel>` in `FlashCudaKernels` - Fixed pre-existing `Device::Cpu` cfg-gate bug in `tensor/creation.rs` - 8 new FA3 backend tests + 6 kernel unit tests; 50 total pass Item 4 — SnapKV attention-score eviction + prefix caching (rtx-inference, rtx-serving-api) - `prefix_index.rs`: `PrefixIndex` with 8MB Zobrist hash table (Knuth MMIX LCG seed), `compute_hash/lookup/insert/remove/remove_page`; 10 unit tests - `eviction.rs`: `AttentionScoreEviction` struct — `accumulate_scores` + `select_evict_positions` (retain top keep_ratio + last recent_window); 7 unit tests - `types.rs`: `EvictionPolicy::AttentionScore { keep_ratio, recent_window }` + `KvCacheConfig::enable_prefix_caching` - `paged_kv_cache.rs`: `prefix_index: Option<PrefixIndex>` + `lookup_prefix / register_prefix / unregister_prefix_page / prefix_caching_enabled` methods - `config.rs` (serving-api): `enable_prefix_sharing: true` (was false), `snapkv_keep_ratio: 0.6`, `snapkv_recent_window: 32` - Fixed 12 pre-existing test errors (spurious `.await` on sync constructors) - 17 SnapKV/prefix tests pass Total: 918 lib tests pass across rtx-tensor, rtx-flash-attention, rtx-transformers, rtx-inference. Zero new failures. Co-Authored-By: Claude Sonnet 4.6 <[email protected]>	2026-06-26 19:56:39 +00:00
Omar SobhandClaude Sonnet 4.6	c82d26d6e7	style: rustfmt formatting pass on rtx-tensor and rtx-flash-attention ... Import reordering, long-line reformatting — no logic changes. Co-Authored-By: Claude Sonnet 4.6 <[email protected]>	2026-06-26 18:11:10 +00:00
Omar SobhandClaude Sonnet 4.6	228137555f	fix(gaps): G0/G2/G5/G8 — eliminate unimplemented! panics, re-enable rtx-distributed, rtx-tts, fix multimodal forward ... G0 (Critical): Replace 45 unimplemented!() panics across three GPU backends - rtx-backend-cuda: sin/cos/tanh via PTX, relu/sigmoid/leaky_relu/elu via activation.rs, pow/clamp/gt_scalar via unary.rs, var/var_dim host-side, conv2d/max_pool2d/avg_pool2d CPU fallback in new ops/conv.rs; new PTX kernels in element_wise.cu - rtx-backend-rocm: all 15 ops via CPU round-trip (to_vec → compute → from_slice) - rtx-backend-sycl: all 15 ops via CPU round-trip (to_host → compute → from_data) G2 (High): Re-add rtx-distributed to workspace - Vendor 4 minimal RNCCL stub crates at crates/vendor/rnccl/* - Update rtx-distributed RNCCL path deps to point at stubs (../../../../RNCCL/* → ../../vendor/rnccl/*) - Remove rtx-distributed from workspace exclude list, add to members G5 (Medium): Re-enable rtx-tts (213 tests restored) - Fix 15 rtx-nn API drift issues: LayerNorm::new, Conv1d::from_config, Conv1dPadding::Zeros, Dropout::new(p, device), tensor methods (relu/tanh/sigmoid/cat/stack), squeeze(Some(n)), to_vec() turbofish removal, Tensor::randn with &[...] slices G8 (Low): Quantum stubs + multimodal forward bug - rtx-timeseries: remove dead quantum/neuromorphic TODO comment blocks (no module files exist) - rtx-multimodal/fusion/transformer.rs: wire TransformerBlock loop in forward() - rtx-multimodal/fusion/strategies.rs: wire bottleneck_layers loop in forward() - rtx-transformers/architectures/transformer_block.rs: add forward() method (pre-norm residuals; full attention+FFN pending when those sub-layers are wired) Co-Authored-By: Claude Sonnet 4.6 <[email protected]>	2026-06-26 13:40:23 +00:00
osobh	5c2ee63d53	GPU Mamba forward + rtx-tensor device-pointer API + matrix exponential ... Persist accumulated WIP across rtx-tensor / rtx-transformers / rtx-runtime. Two related feature groups: GPU enablement (unblocks the Phase-3 spec §8 CUDA Mamba path): - rtx-tensor: `Tensor::cuda_device_ptr()` + storage GPU-buffer accessors (`raw_ptr.rs`) expose the raw CUdeviceptr that kernel launches need — the "rtx-tensor GPU memory access API" the Mamba CUDA kernels were blocked on. - rtx-transformers: `MambaBlock::forward_cuda` runs the four linear projections through cuBLAS on-device (in/out/x/dt_proj), keeping the selective scan + conv1d + activations on CPU; dispatched automatically from `forward` when on a CUDA device under the `cuda` feature. Updated `mamba_cuda_kernels.rs` accordingly. - supporting plumbing in rtx-runtime stream/bridge and rtx-tensor storage/conversion/concatenation/creation + rtx-flash-attention. Linear algebra (rtx-tensor): - `linalg/matrix_exp.rs`: real matrix exponential via scaling-and-squaring with a degree-13 Padé approximant (Higham 2005), f64 internally. - `complex/linalg.rs`: complex matmul/adjoint, Hermitian eigendecomposition (`ComplexEigenResult`), and the complex matrix exponential, nalgebra-backed. - tests for both. Builds verified on the CPU path (`cargo check -p rtx-tensor -p rtx-transformers -p rtx-runtime -p rtx-flash-attention` clean). The `cuda` feature and the rtx-backend-cuda NVCC build remain unbuildable on this host (CUDA/glibc header mismatch) — pre-existing and unrelated to these changes.	2026-06-15 18:51:30 -07:00
Omar SobhandClaude Opus 4.6	0a17f170e6	test(rtx-tensor): add coverage tests for GenericTensor uncovered branches ... Add 10 new tests exercising previously uncovered GenericTensor operations: leaky_relu, elu, gt_scalar, var, var_dim, conv2d (identity kernel, stride, grad propagation), max_pool2d, and avg_pool2d. Also add test_utils.rs module for shared test helpers. SDLC-Coverage: rtx-tensor generic/tensor.rs 19.6% → targeting ~40%+ Co-Authored-By: Claude Opus 4.6 <[email protected]>	2026-05-14 19:25:11 -07:00
3 people	3e3e8819f6	rtx-tensor + rtx-transformers: deterministic init + Mamba weight persistence ... Two coordinated additions for the omni-cortex D249/D250 work: rtx-tensor: Tensor::randn_seeded(shape, device, seed) — like randn() but routes through StdRng::seed_from_u64(seed) so two calls with (shape, device, seed) produce bit-exact identical tensors. CPU is the canonical generator; GPU calls go via to_device transfer. Required for reproducible model init. rtx-transformers: MambaBlock gains: - new_seeded(config, device, seed) — every internal weight tensor initialised via randn_seeded() with per-tensor SplitMix64-derived seeds. Two calls with the same (config, device, seed) → bit- exact identical block. - persistence_tensors() -> Vec<(&'static str, &Tensor)> — read-only view of the six (or seven, with conv_bias) internal weight tensors with canonical names (in_proj, conv1d_weight, conv1d_bias?, A_log, dt_proj, out_proj). Stable across versions so safetensors round-trip works. - from_persistence_tensors(config, device, HashMap<String, Tensor>) — rebuild a MambaBlock from a name → tensor map. Validates each tensor's shape against the config and surfaces clean errors on mismatch (so wrong-DIM safetensors loads fail explicitly). These three primitives together give omni-cortex's D249 (operator- seeded determinism) and D250 (safetensors round-trip + BLAKE3 hash pin) clean library hooks without exposing MambaBlock's private fields. Co-Authored-By: Claude Opus 4.7 (1M context) <[email protected]>	2026-05-04 05:26:27 -07:00
Omar Sobh	16161bb9df	deps: align all 56 per-crate Cargo.toml files to thiserror v2 ... The workspace root was upgraded to thiserror = "2" in an earlier commit, but 56 per-crate Cargo.toml files still independently declared "1.0". These crates do not use workspace.dependencies inheritance for thiserror. All updated to thiserror = "2" for complete fleet alignment. Includes: rtx-backend, rtx-tensor, rtx-losses, rtx-backend-cuda/rocm/metal, all training crates (rtx-auto, rtx-rl, rtx-distributed, rtx-federated, etc.), specialized crates (rtx-science, rtx-platform, rtx-nmf, rtx-neuro-*), production crates (rtx-streaming, rtx-serving-api), and all demo crates. cargo check --workspace: PASSES.	2026-04-26 11:45:14 -07:00
redclawsystems	4d88dc0584	Initial commit	2026-03-04 00:08:42 +00:00