53 Commits

Include renames

Author	SHA1	Message	Date
Omar SobhandClaude Opus 5	796b8487ad	rtx-backend-cuda: native index_select / index_add — HetGAT training 2.5x, inference 4.3x ... The Backend trait's index_select and index_add have default bodies that round-trip through host memory. That is correct everywhere and was the only implementation CUDA had. Graph message passing is made of these two ops, so dg-gnn's HetGAT paid a device->host->device copy per layer per pass and the RTX 5060 Ti sat at ~10% utilisation during training. Design follows rtx-backend-metal's ops::index: gather is one thread per output element; scatter-add walks the CSR of the adjoint selection matrix S^T, built host-side by counting sort, so it needs NO atomics and is deterministic with duplicate indices — the training loss is bit-identical to the host reference. Device index buffers are cached per thread keyed by the exact index list, so a static graph topology uploads once. Two small NVRTC kernels; no cuSPARSE. Measured on dg-gnn, Harris 42,955 links, v8 recipe, RTX 5060 Ti: training batch 8 9,042 -> 3,562 ms/step (2.5x) inference single p50 55.4 -> 12.9 ms (4.3x) inference batch 8 257 -> 20 ms/scen (13x; batching helps again) GPU utilisation median 10% -> 21%, p90 17% -> 43% Tests: gather with repeats, scatter-add with duplicates and untouched rows, the adjoint identity <S x, y> == <x, S^T y> (what autograd relies on), a hub-heavy pattern against the host reference, and the range-check panic. rtx-backend-cuda --features cuda: 60 + 16 passed, 0 failed. Co-Authored-By: Claude Opus 5 <[email protected]>	2026-09-11 23:09:01 -05:00
Omar SobhandClaude Opus 5	4f7b350d96	rtx-backend-cuda: transpose of tall tensors failed to launch, and the generic permute was an identity copy ... Found by running dg-gnn's HetGAT training on an RTX 5060 Ti: the first backward pass panicked in transpose_2d with CUDA_ERROR_INVALID_VALUE. The tensor was a [4,211,136 x 1] gradient. The tiled kernel maps rows onto grid.y, and CUDA caps grid.y at 65,535 blocks, so anything past ~2.1M rows was rejected at launch. Inference never hit it — the forward pass has no transposes. Three fixes, each tested on the GPU: - A row or column vector transposes to itself in memory ([N,1] and [1,N] are the same N floats). swap_dims now shares the buffer and swaps the shape; no kernel. This is the case that actually failed. - transpose_2d_gpu hands matrices with rows/32 > 65,535 to the 1-D generic permute, whose grid.x allows 2^31-1 blocks. - transpose_generic_gpu passed the INPUT's strides (swapped) as the kernel's output_strides — but the kernel DECODES each flat output index with those, so they must be the contiguous strides of the output shape. For a 2-D input that was [1, cols], which decodes every index to itself: the "permute" was a plain copy. Verified against the original code — a [2,3,4] swap_dims(0,2) returned b[1][0][0] = 12.0 where 1.0 is correct. Every higher-D dim swap went through this path; nothing had checked it numerically. Also stamps kernel outputs with the contiguous strides of their new shape rather than the input's strides swapped. Nothing outside ops/shape.rs reads strides today, so that was latent, but is_contiguous() now tells the truth. rtx-backend-cuda --features cuda: 55 + 16 passed, 0 failed (was 51 + 16; four new tests, one of which fails on the original code for each bug above). Co-Authored-By: Claude Opus 5 <[email protected]>	2026-09-11 21:42:27 -05:00
Omar SobhandClaude Fable 5.1	0f578087ce	feat(rtx-interpret): drift-gated decoder renormalisation (SAEConfig::normalize_gate) ... `normalize_gate: Option<(lo, hi)>` — when set, a decoder column is rescaled to unit norm only if its norm has left the band; columns inside are left exactly as the gradient step made them (divisor 1.0). `None` keeps per-step renormalisation, bit for bit. Why (omni-cortex D629/D630): per-step rescaling was measured doing two opposite things on the same 32-unit SAE. With it off, two runs descended cleanly to floors 3-7x LOWER than with it on — it was fighting descent. Two other runs (lr 0.01, seeds 7 and 99) diverged outright without it — it was also the clamp holding an unstable rate finite, turning a blow-up into a slow oscillation that looked like a healthy dictionary drifting. The band keeps the second role and drops the first; D630 measures whether it does both. The cold-start exemption is applied after the gate, unchanged. Test pins: in-band columns bit-identical before/after, out-of-band pulled to unit, gate None == per-step. Fixture norms sit strictly off the band edge — a hand-scaled 2.0 came out 2.0000002 in f32 and was, correctly, treated as outside. Co-Authored-By: Claude Fable 5.1 <[email protected]>	2026-09-02 20:30:25 -07:00
Omar SobhandClaude Opus 5	9575b84803	style: clear the fmt gate and two lib clippy warnings ... Deferred deliberately while the TWIN-2B/2C campaign had live marches: each march is a fresh `cargo test` invocation, so reformatting `turek_hron_fsi2.rs` mid-campaign would have forced a test-binary rebuild and cost comparability for a cosmetic gate. The family closed, so this is now free. - `cargo fmt --all` across 8 files that had drifted (including the FSI2/FSI3 harnesses touched by the UMEAN/ES override commits). - `rtx-feature-store/tests/integration_tests.rs` had trailing whitespace rustfmt refused to format around ("left behind trailing whitespace" internal error), so the whole file was being skipped; stripped it and the file formats now. - Two `unnecessary_parentheses` warnings in the rtx-transformers lib (`continual/progressive.rs`, `curriculum/mod.rs`) — these were the only rustytorch warnings surfacing through omni-cortex's workspace clippy gate, which is how they were found. No behaviour change. rtx-fsi test binaries still build. Co-Authored-By: Claude Opus 5 (1M context) <[email protected]> Claude-Session: https://claude.ai/code/session_01B1feFAQxjbCRHePUdxuNra	2026-09-02 19:15:53 -07:00
Omar SobhandClaude Fable 5	328f65233e	rtx-interpret: decoder cold-start window for reinitialized SAE units ... reinitialize_encoder_neuron_cold / SAETrainer::reinitialize_neuron_cold exempt a freshly reset unit's decoder column from per-step normalize_decoder for cold_steps training steps, so its small random init is not blown up to unit norm before it has learned anything — the mechanism omni-cortex's D605 refutation left as the prime suspect, now testable (D620 downstream). Runtime-only state, not carried through checkpoints (documented); cold_steps 0 is exactly the plain reinit, and existing entry points delegate with 0. Co-Authored-By: Claude Fable 5 <[email protected]> Claude-Session: https://claude.ai/code/session_01B1feFAQxjbCRHePUdxuNra	2026-08-30 08:31:08 -05:00
Omar SobhandClaude Fable 5	366a46b471	rtx-interpret: seeded SAE init + coupled per-unit optimizer reset ... SparseAutoencoder::new_seeded draws encoder/decoder weights via randn_seeded with per-tensor SplitMix64-derived seeds (same derivation as MambaBlock::new_seeded), so identical (config, seed) gives bit-exact SAEs — without it, cross-instance loss comparisons are noise (measured downstream: 0.09 vs 0.65 starts on identical data). SAETrainer::reinitialize_neuron couples the encoder-unit weight reinit with zeroing that unit's optimizer moment rows (encoder row, bias slot, decoder column), so external generate-and-test callers can't reset weights while leaving optimizer state stale — previously only the trainer's internal dead-neuron resampling did both. Note train_step's update rule is plain SGD today, so the moment reset is inert until the Adam path is switched on; the coupling is the contract either way, and a doctored-checkpoint test pins the row/column semantics. Also drops a vacuous assert!(true) smoke test that failed clippy's assertions_on_constants. Co-Authored-By: Claude Fable 5 <[email protected]> Claude-Session: https://claude.ai/code/session_01B1feFAQxjbCRHePUdxuNra	2026-08-28 20:49:11 -05:00
quantumandClaude Fable 5	c36cf2f8a7	rtx-backend-metal: fix swap_dims returning a corrupt strided view ... swap_dims copied the buffer but wrote elements back at their ORIGINAL positions (new_idx was computed with the swapped strides), returning a stride-swapped non-contiguous tensor. Every other op in this backend — elementwise kernels, MPS matmul, to_vec — reads raw buffers and ignores strides, so any transpose consumer (notably the autograd matmul backward, grad_a = grad_c @ b^T) silently computed on untransposed data. Found via CPU-vs-Metal gradient parity on the DigiGraph HetGAT: forward matched, gradients were ~2x off. swap_dims now physically permutes into a contiguous result (reading through the input's strides + offset), and reshape asserts contiguity instead of silently reinterpreting a non-contiguous buffer. 3 new parity tests incl. matmul-after-transpose (25 total pass on-device). Co-Authored-By: Claude Fable 5 <[email protected]>	2026-08-21 06:11:38 -07:00
quantumandClaude Fable 5	9297976929	rtx-backend-metal: GPU index_select / index_add via one-hot CSR SpMM ... Override the Backend trait's host-round-trip defaults: gather is S @ X with S the [E x N] one-hot selection CSR; scatter-add is the adjoint S^T @ X, whose CSR is built directly by counting sort so duplicate indices land in one row and the spmm kernel (one thread per output element) accumulates them without atomics. CSR matrices are cached per thread keyed by the exact index list + dims, so a static graph topology (GNN message passing) builds each matrix once. Host fallback on degenerate shapes or any sparse-pipeline failure. 13 new parity tests vs CPU reference: duplicates, unreferenced rows, D=1/2/3, 15k x 5k x 64 gather/scatter, cache reuse, adjoint roundtrip. Verified on-device that the SpMM path (not the fallback) serves all 13. Co-Authored-By: Claude Fable 5 <[email protected]>	2026-08-21 05:56:23 -07:00
quantumandClaude Fable 5	2e23d0f4c6	rtx-backend: gate CUDA parity tests to x86_64 Linux ... The rtx-backend-cuda dev-dependency is already gated to cfg(all(linux, x86_64)) in Cargo.toml, but the test file imported it unconditionally, so cargo test -p rtx-backend failed to compile on macOS. Co-Authored-By: Claude Fable 5 <[email protected]>	2026-08-21 05:52:03 -07:00
quantumandClaude Fable 5	72b41e3167	rtx-backend-metal: align to current rtx-metal API ... rtx-metal dropped tensor_ops::{sin,cos,pow,clamp,gt_scalar,var} and never had nn::{max_pool2d,avg_pool2d}; nn::conv2d grew a scalar 14-arg signature. Give the missing ops correct host fallbacks (the sum_dim pattern), and dispatch conv2d to the Metal kernel when its restricted signature applies (symmetric stride/padding, dilation 1, groups 1), host fallback otherwise. cargo test -p rtx-backend-metal: 22/22 parity tests pass on-device (M5). Co-Authored-By: Claude Fable 5 <[email protected]>	2026-08-21 05:52:03 -07:00
Omar SobhandClaude Fable 5	38645c7c74	fix(autograd): AbsBackward produced NaN for exactly-zero inputs ... sign was computed as x/|x|, which is 0/0 = NaN at x = 0; one zero element in an |pred - target| loss poisoned every upstream gradient (hit deterministically by dg-gnn HetGAT training). Compute x/(|x| + tiny) instead so sign(0) = 0 (the subgradient convention). Regression test included. Co-Authored-By: Claude Fable 5 <[email protected]>	2026-08-20 11:53:30 -07:00
Omar SobhandClaude Fable 5	67c47898fa	perf(backend-cpu): parallelize blocked gemm over row blocks with rayon ... Each task owns a disjoint BLOCK_SIZE-row slice of the result; the inner blocked kernel is unchanged. Needed for dg-gnn HetGAT training throughput (node-level [M,64]x[64,64] matmuls dominated single-threaded step time). Co-Authored-By: Claude Fable 5 <[email protected]>	2026-08-20 11:37:43 -07:00
Omar SobhandClaude Fable 5	9969d8a661	feat(backend): add differentiable index_select / index_add row ops ... Add two row-indexing ops along dim 0 to the `Backend` trait so gather / scatter-add message passing (GNNs, segment softmax, bias tiling) can be trained through `Autodiff<B>`: - `index_select(tensor, indices)` — out[i, ..] = tensor[indices[i], ..] - `index_add(tensor, indices, num_rows)` — out = zeros; out[idx[i], ..] += tensor[i, ..] They are each other's adjoint, which is what the backward passes use. Both trait methods have default bodies (host round-trip via to_data / from_data) so every existing backend keeps compiling and is correct; backends override with native kernels: - rtx-backend-cpu: new ops/index.rs (rayon-parallel gather over output rows above a size threshold, sequential deterministic scatter-add), wired into CpuBackend and CpuBackendF64, with unit tests for D=1/2/3, duplicates, untouched rows, empty inputs, bounds panics and adjointness. - rtx-autograd: Autodiff<B> overrides both ops and records IndexSelectBackward / IndexAddBackward (new ops/index.rs); finite- difference gradchecks on the real CpuBackend cover repeated-index accumulation, untouched-row zero grads, bias tiling via index_select of a [1,F] row, and a full per-segment softmax. - rtx-fusion: forward both ops to the inner backend. Co-Authored-By: Claude Fable 5 <[email protected]>	2026-08-20 11:05:42 -07:00
osobhandClaude Sonnet 5	4aaa36a57a	style: cargo fmt --workspace (whitespace/wrapping only, no semantic change) ... Whole-workspace rustfmt pass picked up while iterating on Mamba GPU backward work. Verified formatting-only via diff sampling; no logic changed. Co-Authored-By: Claude Sonnet 5 <[email protected]>	2026-08-10 07:09:36 -07:00
osobhandClaude Fable 5	0cbfc1a739	fix(tests): repair rtx-onnx-codegen build and all pre-existing test failures in rtx-serving-api and rtx-runtime ... - rtx-onnx-codegen: re-export AttributeValue from ir (private-module import broke the whole crate; remaining errors were knock-ons). - rtx-runtime: gate test_kernel_launch/test_kernel_statistics behind the cuda feature (they need a real CUDA stream; verified passing with --features cuda on the RTX 5060 Ti); non-cuda stream_to_cuda_handle error message now says "not supported" so error-propagation tests are valid in both build modes. - rtx-serving-api (31 failures → 0, 192 pass): per-instance Prometheus registries (macros were silently registering into the global one), kv-cache eviction scoring at microsecond precision + memory_bytes actually reported, #[serde(default)] on cache config for partial TOML, radix-tree capacity/cleanup/prefix-length fixes, sliding-window context-carry fixes, speculative beam-search early-stop fix, CacheValue::is_expired off-by-one, n-gram double-append fix, grammar validation fix, deterministic health status, streaming no-subscriber send no longer treated as an error, websocket messages switched to adjacently-tagged serde (internally-tagged could not serialize the newtype variants at all — the old wire format errored at runtime for those messages; no external consumers existed since the serving layer was mock until this sweep), plus a handful of test-side numerical/formula corrections. Co-Authored-By: Claude Fable 5 <[email protected]>	2026-07-09 19:49:01 -07:00
osobhandClaude Fable 5	5f32165184	chore(sweep): delete 43 orphaned source files; document SYCL/demo/duplication status ... Deletions (all verified unreferenced by any mod/include/path declaration; git history preserves them): - rtx-transformers: entire orphaned curriculum/ split (mod.rs holds the real inline implementation), non-_simple graph variants, superseded simmim/jepa_integration files, layers/{sliding_window_attention, positional_encoding,ssm_state_cache_original}, lib_full/lib_minimal/ error_full/error_minimal, orphaned MoE impls (moe_layer, moe_integration). - rtx-distributed/parallel_old.rs; rtx-flash-attention/{core_full, lib_full}.rs; rtx-compress legacy_distillation + structured_pruner. - rtx-tensor/tensor_core.rs; rtx-runtime/{cuda_kernel_ops, cuda_backend_mock}.rs; rtx-memory/{gpu_pool_manager,allocator, pool_type}.rs; rtx-losses/{lib_minimal,lib_full}.rs. Docs honesty: - rtx-backend-sycl marked EXPERIMENTAL SKELETON in crate docs and CLAUDE.md backend table (all ops return NotImplemented). - docs/consolidation.md records canonical MoE (layers/mixture_of_experts) and flash-attention (rtx-flash-attention crate) implementations plus remaining duplicates to consolidate. - CLAUDE.md: meta-crate GPU features noted; simulation-only demos named; serving/streaming mock removal noted. Verified: cargo check --workspace clean (rtx-onnx-codegen pre-broken at HEAD, unrelated); lib tests pass for all touched crates (rtx-runtime's 4 failures pre-exist at HEAD). Co-Authored-By: Claude Fable 5 <[email protected]>	2026-07-09 19:32:21 -07:00
osobhandClaude Fable 5	1e3c604896	feat(meta,jepa): expose GPU features through meta-crates; wire JEPA cluster plan and real shard loading ... Meta-crates (Phase 2): - rtx-core / rtx-training / rtx-inference-stack gain cuda and metal features threading into their sub-crates; GPU was previously unreachable through the user-facing bundles. - rtx-training restores rtx-distributed (the hpc-channels blocker is gone) so the advertised DistributedTransformerTrainer resolves; drops the unused rtx-runtime dep. - rtx-transformers drops unused rtx-backend/rtx-backend-cpu deps (stale comment referenced a teacher that never used them). Never-compiled CUDA paths fixed (surfaced by the new feature wiring, verified on RTX 5060 Ti / CUDA 13.1): - rtx-compress build.rs: missing Path/Command/fs imports. - rtx-flash-attention flash_decode_forward: reborrow &mut kernel args. - rtx-transformers: rope kernel include path, cudarc 0.18 Arc<CudaModule>, PushKernelArg imports in jepa_gpu, edition-2024 ref patterns. - rtx-memory: full cudarc 0.18 port (CudaContext, stream-based alloc, DevicePtr accessors, error enum formatting) across gpu_pinning, gpu_transfer, gpu_real, gpu_allocator/arena, gpu_tests. JEPA (Phase 3): - JepaRunConfig::apply_cluster_plan consumes ClusterTrainingPlan (batch size, TP/DP, world size, total steps) so jepa_cluster is no longer standalone dead config; ViTSizeStr::approx_params_m feeds JepaParallelConfig::for_model_and_cluster. - WebDatasetShard::load reads real .tar shards from disk via the existing parser (gzip rejected explicitly); to_in_memory documented as synthetic/test-only. - New image-decode feature actually defines the dep for the previously unreachable cfg(feature = "image-decode") JPEG/PNG decode path. Co-Authored-By: Claude Fable 5 <[email protected]>	2026-07-09 19:25:51 -07:00
osobhandClaude Opus 4.8	63776aa0f2	fix(rtx-backend): gate CUDA dev-dep to x86_64-linux so cargo test works on macOS ... rtx-backend's only build-graph CUDA pull was a [dev-dependencies] entry (rtx-backend-cuda with features=[cuda]) compiled unconditionally, so cargo test --workspace failed on macOS/non-CUDA hosts trying to build cudarc. Gate it to x86_64 Linux (where the CUDA toolkit lives); cargo build was unaffected. Also drop the no-op cuda from rtx-nlg default features (empty placeholder that misleadingly implied CUDA-by-default). Audit: 121/126 workspace crates already gate CUDA correctly (optional + non-default). Co-Authored-By: Claude Opus 4.8 <[email protected]>	2026-06-27 09:07:14 -07:00
osobhandClaude Opus 4.8	e8a2036db4	fix(ci,rtx-tensor): resolve clippy --all-features intel-mkl conflict; gate MKL to x86_64-linux ... clippy --all-features enabled both rtx-tensor/mkl (intel-mkl-src mkl-static-lp64-seq) and rtx-csm/candle mkl (mkl-static-lp64-iomp) -> two conflicting intel-mkl-src link configs -> E0428 'MKL_CONFIG defined multiple times'. - clippy: drop --all-features (lint default features; --all-features is unsound for a multi-platform, mutually-exclusive-backend workspace). - rtx-tensor: gate intel-mkl-src to cfg(all(target_os=linux, target_arch=x86_64)) so mkl is never pulled on macOS/arm. Co-Authored-By: Claude Opus 4.8 <[email protected]>	2026-06-27 08:12:27 -07:00
Claude CodeandClaude Opus 4.8	df6ce1ce22	feat(rtx-nn): genericize the layer library over B::FloatElem (f64-capable) ... Phase 4b of the rustytorch f32→f64 plan. Relaxed ~36 `impl<B: Backend<FloatElem = f32>>` blocks across 7 layer files to `impl<B: Backend>` over B::FloatElem: normalization (LayerNorm/RMSNorm), activation (LeakyReLU/ELU), dropout (1d/2d/3d), embedding, attention (MultiHeadAttention), transformer (MLP/Block/Encoder), conv (Conv1d/2d). Config scalars stay f32 and convert via B::FloatElem::from_f32; the layers delegate to the already-generic GenericTensor ops. f32 numerics byte-identical. The whole common rtx-nn layer library now runs on CpuBackendF64. Validated: 334 f32 lib tests (no regression) + 2 capstone + 3 new f64 layer smoke tests (layer_norm/conv2d/attention on CpuBackendF64) pass; QPUDIDP surrogate still compiles; clippy clean. Remaining f32-gated: batch_norm (GenericBatchNorm1d/2d/GroupNorm) — its manual mean/variance arithmetic needs a `where B::FloatElem: num_traits::Float` bound; focused follow-on. (Plus rtx-autograd's f32 tape, the deep-re-architecture item.) Co-Authored-By: Claude Opus 4.8 (1M context) <[email protected]>	2026-06-26 23:07:52 -07:00
Claude CodeandClaude Opus 4.8	c28a848250	feat(rtx-nn): f64-capable GenericLinear + f64 MLP gradient-precision capstone ... Phase 4/5 of the rustytorch f32→f64 plan. GenericLinear's 3 `impl<B: Backend<FloatElem = f32>>` blocks relaxed to `impl<B: Backend>` (from_weights takes &[B::FloatElem]; Xavier scale via B::FloatElem::from_f64), so a Linear→ReLU→Linear MLP runs end-to-end on CpuBackendF64. f32 backward-compat holds via B::FloatElem = f32. Capstone (tests/f64_mlp_precision.rs): a 4→8→1 MLP gradient checked vs central finite differences — f64 err 6.99e-12 (≤1e-9) vs f32 err 1.01e-2, i.e. f64 ~1.45e9× more accurate. This is the quantum-precision-gradient win that motivated the migration. Validated: rtx-nn 334 f32 lib tests + 2 new f64 capstone tests pass; rtx-autograd builds + tests pass; **QPUDIDP qpu-didp-surrogate compiles + 15 tests pass** (uses GenericLinear). clippy clean. Scope note: rtx-autograd's reverse-mode tape stores f32 concretely (backward()->HashMap<_,Vec<f32>>) — making it f64 is a deep tape re-architecture, not a constraint relaxation, so it's a documented follow-on (no current consumer uses it; QPUDIDP hand-rolls f64 backprop). Other rtx-nn layers (conv/transformer/attention/...) remain f32-gated — same mechanical relaxation, follow-on. Co-Authored-By: Claude Opus 4.8 (1M context) <[email protected]>	2026-06-26 22:36:23 -07:00
Claude CodeandClaude Opus 4.8	a25f24494c	feat(rtx-tensor): genericize GenericTensor over B::FloatElem (f64-capable) ... Phase 2 of the rustytorch f32→f64 plan. All 6 `impl<B: Backend<FloatElem = f32>>` blocks on GenericTensor relaxed to `impl<B: Backend>`, with concrete f32 → B::FloatElem (full/from_slice/to_vec/add_scalar/mul_scalar/pow/clamp/leaky_relu/ elu/layer_norm/rms_norm). The genericization was fully clean — every Backend trait scalar param was already Self::FloatElem, so no methods had to stay f32-gated. GenericTensor now works with CpuBackendF64 as well as CpuBackend. Backward-compat holds via B::FloatElem = f32 for CpuBackend: to_vec() still returns Vec<f32>, from_slice still takes &[f32]. Validated: 706 rtx-tensor tests pass (704 f32 + 2 new f64); the f64 test proves 1+2^-30 survives through from_slice/matmul/to_vec (f32 rounds to 1.0). rtx-nn builds; **QPUDIDP's qpu-didp-surrogate (external, ~125 f32 sites) still compiles**. clippy clean. Co-Authored-By: Claude Opus 4.8 (1M context) <[email protected]>	2026-06-26 22:28:26 -07:00
Claude CodeandClaude Opus 4.8	97ef5efe0b	feat(rtx-backend-cpu): generic ops over element type + coexisting CpuBackendF64 ... Phase 1 of the rustytorch f32→f64 plan, backend layer. All 11 ops modules (basic/creation/unary/gemm/reduction/activation/shape/conv/pooling/normalization/ attention) are now generic over the element via a `CpuFloat` bound (`num_traits::Float + Send + Sync + 'static`); f32/Vec<f32> → E/Vec<E>, literals → E::zero()/one()/from(..). The ops were already pure scalar + rayon (no SIMD), so the f32 path is byte-identical (E inferred as f32 under CpuBackend) — no SIMD/BLAS dual-path needed. Adds `CpuBackendF64` (FloatElem = f64, TensorPrimitive = CpuTensorPrimitive<D,f64>) delegating to the same generic ops, plus the DeviceOps<CpuBackendF64> impl. CpuBackend (f32) untouched. Validated: 35 tests pass (33 original f32 + 2 new f64); `cpu_backend_f64_exceeds_ f32_precision` preserves 1+2^-30 (f32 rounds to 1.0) — proves genuine f64. rtx-tensor (dependent) still builds. clippy clean. Co-Authored-By: Claude Opus 4.8 (1M context) <[email protected]>	2026-06-26 22:08:18 -07:00
osobh	c57140ffe4	Merge branch 'feat/f64-cpu-precision'	2026-06-26 21:22:40 -07:00
Claude CodeandClaude Opus 4.8	85f2678963	feat(rtx-backend-cpu): make CpuTensorPrimitive generic over element type ... Foundation for a coexisting f64 CPU backend (CpuBackendF64) per the rustytorch f32→f64 plan. CpuTensorPrimitive<const D> becomes CpuTensorPrimitive<const D, E = f32>: storage is Vec<E>, inherent methods (new/data/data_mut/to_vec) are element-generic. The `E = f32` default keeps every existing `CpuTensorPrimitive<D>` reference (the ops layer, the Backend GAT) f32-identical — fully backward-compatible. Send/Sync bounds are conditioned on E. 33 tests pass, clippy clean. Next: genericize the ops over the element (preserving the f32 SIMD path), add CpuBackendF64, then relax rtx-tensor's `FloatElem = f32` impl constraints. Co-Authored-By: Claude Opus 4.8 (1M context) <[email protected]>	2026-06-26 21:21:53 -07:00
Omar SobhandClaude Sonnet 4.6	ef786c0ab1	feat(batch5): mid-batch injection, PagedAttn v2 defrag, fused RoPE kernel ... Continuous batching (rtx-serving-api): - ContinuousBatchingConfig: enable_mid_batch_injection (default true), injection_check_interval (default 1), max_injections_per_step (default 4) - ContinuousBatchingController: inject_into_active_batch() + try_inject_pending() allow new sequences to join a running decode batch after each step - BatchingError::BatchFull variant; 3 new tests PagedAttention v2 defrag (rtx-memory): - PageTable::fragmentation_ratio() — hole-counting (sandwiched free pages / total) - PageTable::defragment() — in-place left-compaction of physical page metadata, consistent lock order (free_pages -> physical_pages -> sequences); GPU KV copy stub comment; DefragStats return value; re-exported from lib.rs - 4 defrag tests; fixed 2 pre-existing compile errors in gpu_oom.rs + gpu_transfer.rs - 192 tests pass Fused RoPE kernel (rtx-transformers): - build_cos_sin_table() + rope_forward_cpu() CPU reference (norm-preserving) - RopeFusedKernel wrapper; rope_forward.cu CUDA kernel (1 block per (B,H,T), 1 thread per dim pair, NVRTC compiled) - Replaced apply_rope_rotation() mul_scalar(0.99) stub with real pairwise rotation - build.rs for NVRTC kernel tracking; layers/mod.rs wired; 8 tests pass Co-Authored-By: Claude Sonnet 4.6 <[email protected]>	2026-06-27 01:40:47 +00:00
Omar SobhandClaude Sonnet 4.6	311eb23dbd	feat(perf): GPU perf batch 3 — W4A16 AWQ matmul, FSDP2 hooks, RMSNorm+SwiGLU fused kernel ... W4A16 AWQ on-the-fly dequantize+GEMM (rtx-compress) - `w4a16_matmul.rs`: `AWQQuantizedWeightExt` trait + `matmul_cpu()` — group-aligned inner loop, f64 accumulation, low-nibble-first INT4 unpacking matching mx_kernels.cu - `cuda_kernels/w4a16_gemm.cu`: `w4a16_dequant_gemm` kernel, one thread per (batch, out_col), 8-INT4-per-iteration inner loop with `__ldg()` cache hints, BF16 scale decode, f32 accumulate - `quantization/mod.rs`: exports `w4a16_matmul_cpu`, `AWQQuantizedWeightExt` - Fixed 2 pre-existing pruning compile errors - 12 tests: nibble unpack, identity weights, shape, vs-dequant (tol=1e-3), batch=1, zeros FSDP2 forward/backward hooks (rtx-distributed) - `fsdp2.rs`: `update_local_shard()` on `Fsdp2ShardedParam`; sync `all_gather()` + `reduce_scatter_gradient()` using `ProcessGroup::{all_gather,reduce_scatter}` - `pre_forward_hook()` — all-gathers every param (or copies shard in single-process) - `post_backward_hook()` — reduce-scatters gradients, zero_grad, re-shards cache - `step(optimizer_fn)` — applies optimizer closure to each local shard - `make_fsdp2_module()` top-level factory; `Fsdp2MemoryStats` gains 5 new fields incl. `memory_reduction_ratio ≈ world_size` - 6 new tests (end-to-end training step included); total 444 pass RMSNorm+SwiGLU fused CUDA kernel (rtx-fusion) - `cuda/rms_norm_swiglu_fused.cu`: `rms_norm_kernel` + `rms_norm_swiglu_fused`; shared-mem warp reduction (block_x floats), launch: grid=(batch,1,1), block=(min(hidden,1024),1,1) - `cuda_kernels/rms_norm_fused.rs`: CPU reference `rms_norm_cpu`/`swiglu_cpu`/ `rms_norm_swiglu_cpu`; `#[cfg(feature="cuda")] RmsNormFusedKernel` NVRTC wrapper - `codegen/cubecl.rs`: replaced RmsNorm comment stub with cfg-gated NVRTC dispatch - `backend.rs` + `tensor.rs`: added 15 missing `Backend` trait impls (sin/cos/relu/conv2d/…) that blocked test compilation - `Cargo.toml`: added rtx-fusion to workspace members - 8 new tests (PyTorch-formula verified: x=[1,2,3,4] → [0.365, 0.730, 1.095, 1.461]); total 103 pass Test results: 12 + 444 + 103 = 559 tests, 0 failures Co-Authored-By: Claude Sonnet 4.6 <[email protected]>	2026-06-27 00:18:20 +00:00
Omar SobhandClaude Sonnet 4.6	082a50e3a0	feat(perf): GPU perf batch 1 — wire GPU execution paths for FP8, FA3, CUDA Graphs, SnapKV ... FP8 GPU FFI (rtx-tensor) - `fp8_cast.rs`: replaced `not_implemented` stubs with real cudarc 0.18.2 PTX launches; `cast_bf16_to_fp8_e4m3` and `cast_fp8_e4m3_to_bf16` now dispatch to NVCC-compiled `fp8_cast.ptx` via `LazyLock` module cache, matching the `inplace_ops` pattern - `build.rs`: `create_dummy_ptx` now emits `fp8_cast.ptx` alongside `element_wise.ptx` so `include_str!` resolves cleanly when NVCC is absent FlashAttention-3 typed kernel launch (rtx-flash-attention) - `flash_v3_forward.rs`: `forward()` now takes typed `CudaSlice<bf16>` Q/K/V/O + `CudaSlice<f32>` LSE buffer; dispatches via `stream.launch_builder` with block_dim=(128,1,1), grid_dim=(ceil(seq_len/64), batch*heads, 1), shared_mem_bytes=0 (PTX metadata-resolved) - `simple.rs`: added `has_flash_v3()` + `flash_attention_v3_forward_raw()` dispatch - `Cargo.toml`: `half` added as optional cuda-gated dependency CUDA Graphs stream threading (rtx-transformers) - `training_loop.rs`: added `cuda_stream: Option<CudaStreamHandle>` field; `set_cuda_backend()` now creates a non-default capture stream; capture step calls real `begin_capture(stream)` + `end_capture(stream)`; added `set_cuda_stream()` override; replay unchanged (no stream needed) SnapKV + prefix cache BatchScheduler wiring (rtx-inference) - `scheduler.rs`: added `prefix_hit_pages: Option<Vec<PageId>>` + `evicted_positions: Vec<usize>` to `SchedulerRequest`; `BatchScheduler` gains `kv_cache` + `snapkv_eviction` fields; `submit_request` does non-blocking `try_lock` prefix lookup; added `notify_prefill_complete` (registers prefix + runs `select_evict_positions`), `set_kv_cache`, `set_snapkv_eviction`, `get_evicted_positions`, `get_prefix_hit_pages` — +5 new integration tests Test results: 22 + 42 + 75 + 102 = 241 tests, 0 failures Co-Authored-By: Claude Sonnet 4.6 <[email protected]>	2026-06-26 20:39:58 +00:00
Omar SobhandClaude Sonnet 4.6	1eb89c5b2b	feat(perf): GPU perf batch 1 — FP8, FA3 Blackwell, CUDA Graphs, SnapKV, prefix cache ... Item 1 — CUDA Graphs wiring (rtx-transformers) - Added `enable_cuda_graphs: bool` (default false) + `cuda_graph_warmup_iters: usize` (default 3) to `TrainingConfig` - Wired 3-phase state machine into `training_loop.rs` (warmup → capture → replay) gated on `#[cfg(feature = "cuda")]`; stream plumbing stubbed with TODO pending `CudaStreamHandle` threading Item 2 — FP8 E4M3/E5M2 training infrastructure (rtx-tensor, rtx-transformers) - `fp8_cast.cu`: dual-path CUDA kernels — SM_89+ uses `<cuda_fp8.h>` native `__nv_cvt_*` intrinsics; older SM uses software bit-manipulation fallback - `fp8_cast.rs`: host-side CPU casting + `#[cfg(feature = "cuda")]` GPU stubs - `fp8_gemm.rs`: bit-accurate E4M3 decoder/encoder, BF16 round-trip utils, CPU reference matmul with cuBLASLt GPU path documented inline; 12 unit tests - `training_config.rs`: `fp8_training: bool`, `fp8_e4m3_forward: bool` - `linear.rs` (modular): `fp8_mode: bool` field + forward dispatch stub - build.rs: registers `fp8_cast.cu` alongside existing `element_wise.cu` - 22 FP8 unit tests — all pass Item 3 — FlashAttention-3 Blackwell (WGMMA + TMA + warp specialization) - `flash_attention_v3_forward.cu`: SM_90+ warp-specialised producer/consumer kernel (producer TMA-loads K/V tiles, consumers run WMMA as portable WGMMA proxy); SM_89+ FP8 header path; SM<90 standard FA2-style WMMA fallback - `flash_v3_forward.rs`: NVRTC wrapper (`compile_ptx` via `include_str!`), `FlashV3ForwardKernel::new/is_supported/forward`; 6 unit tests - `backend_selector.rs`: `SdpaBackend::FlashAttentionV3`, `for_compute_capability`, `supports_flash_v3` (major >= 9), FA3 scoring (0.98/0.90/0.70), 2× speedup estimate - `kernels/simple.rs`: `v3_kernel: Option<FlashV3ForwardKernel>` in `FlashCudaKernels` - Fixed pre-existing `Device::Cpu` cfg-gate bug in `tensor/creation.rs` - 8 new FA3 backend tests + 6 kernel unit tests; 50 total pass Item 4 — SnapKV attention-score eviction + prefix caching (rtx-inference, rtx-serving-api) - `prefix_index.rs`: `PrefixIndex` with 8MB Zobrist hash table (Knuth MMIX LCG seed), `compute_hash/lookup/insert/remove/remove_page`; 10 unit tests - `eviction.rs`: `AttentionScoreEviction` struct — `accumulate_scores` + `select_evict_positions` (retain top keep_ratio + last recent_window); 7 unit tests - `types.rs`: `EvictionPolicy::AttentionScore { keep_ratio, recent_window }` + `KvCacheConfig::enable_prefix_caching` - `paged_kv_cache.rs`: `prefix_index: Option<PrefixIndex>` + `lookup_prefix / register_prefix / unregister_prefix_page / prefix_caching_enabled` methods - `config.rs` (serving-api): `enable_prefix_sharing: true` (was false), `snapkv_keep_ratio: 0.6`, `snapkv_recent_window: 32` - Fixed 12 pre-existing test errors (spurious `.await` on sync constructors) - 17 SnapKV/prefix tests pass Total: 918 lib tests pass across rtx-tensor, rtx-flash-attention, rtx-transformers, rtx-inference. Zero new failures. Co-Authored-By: Claude Sonnet 4.6 <[email protected]>	2026-06-26 19:56:39 +00:00
Omar SobhandClaude Sonnet 4.6	c82d26d6e7	style: rustfmt formatting pass on rtx-tensor and rtx-flash-attention ... Import reordering, long-line reformatting — no logic changes. Co-Authored-By: Claude Sonnet 4.6 <[email protected]>	2026-06-26 18:11:10 +00:00
Omar SobhandClaude Sonnet 4.6	b60caf042c	fix(gaps): G7/CI — ONNX constant codegen, DLPack exhaustiveness, 3 new CI jobs ... G7 (Low): - rtx-onnx-codegen: replace todo!("Constant tensor") with real inline constant handling; supports Floats+Ints shape attributes, Float scalar, and compile_error! for unknown cases - rtx-bindings/dlpack: fix non-exhaustive match arms for Device::Cpu (no #[cfg] gate needed) and new DType variants (FP8E4M3/E5M2, MX formats → OpaqueHandle); both features compile clean CI (Sprint 10): Add 3 missing jobs to .gitea/workflows/ci.yml - python-bindings: maturin develop --features python on ubuntu + macos - wasm-build: cargo build --target wasm32-unknown-unknown + <5MB size check - distributed-tests: cargo test -p rtx-distributed - ci-success gate now requires all 8 jobs to pass Co-Authored-By: Claude Sonnet 4.6 <[email protected]>	2026-06-26 16:10:22 +00:00
Omar SobhandClaude Sonnet 4.6	448c0a0be5	fix(gaps): G1 — re-enable Python bindings (PyO3 0.25, Python 3.14) ... - Upgrade workspace pyo3 0.24 → 0.25 and numpy 0.24 → 0.25 for Python 3.14 support - rtx-sklearn-py: replace pinned pyo3 0.20 / pyo3-asyncio 0.20 / numpy 0.20 with workspace versions; remove broken pyo3-asyncio async feature; update pyo3-build-config to 0.24 - rtx-bindings: uncomment pyo3/numpy/ndarray optional deps; enable python feature in Cargo.toml - Migrate rtx-bindings python/ to PyO3 0.25 Bound API: &PyAny → Bound<'py, PyAny>, downcast/extract on Bound types, remove rtx_runtime import, remove InferenceError arm (variant not in enum), fix py_shape_to_shape signature - Migrate rtx-sklearn-py src/ to PyO3 0.25 Bound API: #[pymodule] fn now takes &Bound<'_, PyModule>, &PyDict → &Bound<'py, PyDict>, from_array returns Bound (unbind instead of to_owned), PyTuple::new now fallible, use numpy::ndarray (0.16) over workspace ndarray (0.15) to resolve trait mismatches Co-Authored-By: Claude Sonnet 4.6 <[email protected]>	2026-06-26 13:55:09 +00:00
Omar SobhandClaude Sonnet 4.6	228137555f	fix(gaps): G0/G2/G5/G8 — eliminate unimplemented! panics, re-enable rtx-distributed, rtx-tts, fix multimodal forward ... G0 (Critical): Replace 45 unimplemented!() panics across three GPU backends - rtx-backend-cuda: sin/cos/tanh via PTX, relu/sigmoid/leaky_relu/elu via activation.rs, pow/clamp/gt_scalar via unary.rs, var/var_dim host-side, conv2d/max_pool2d/avg_pool2d CPU fallback in new ops/conv.rs; new PTX kernels in element_wise.cu - rtx-backend-rocm: all 15 ops via CPU round-trip (to_vec → compute → from_slice) - rtx-backend-sycl: all 15 ops via CPU round-trip (to_host → compute → from_data) G2 (High): Re-add rtx-distributed to workspace - Vendor 4 minimal RNCCL stub crates at crates/vendor/rnccl/* - Update rtx-distributed RNCCL path deps to point at stubs (../../../../RNCCL/* → ../../vendor/rnccl/*) - Remove rtx-distributed from workspace exclude list, add to members G5 (Medium): Re-enable rtx-tts (213 tests restored) - Fix 15 rtx-nn API drift issues: LayerNorm::new, Conv1d::from_config, Conv1dPadding::Zeros, Dropout::new(p, device), tensor methods (relu/tanh/sigmoid/cat/stack), squeeze(Some(n)), to_vec() turbofish removal, Tensor::randn with &[...] slices G8 (Low): Quantum stubs + multimodal forward bug - rtx-timeseries: remove dead quantum/neuromorphic TODO comment blocks (no module files exist) - rtx-multimodal/fusion/transformer.rs: wire TransformerBlock loop in forward() - rtx-multimodal/fusion/strategies.rs: wire bottleneck_layers loop in forward() - rtx-transformers/architectures/transformer_block.rs: add forward() method (pre-norm residuals; full attention+FFN pending when those sub-layers are wired) Co-Authored-By: Claude Sonnet 4.6 <[email protected]>	2026-06-26 13:40:23 +00:00
Omar SobhandClaude Sonnet 4.6	32c4def075	D310: enable rtx-backend-cuda for Blackwell sm_120 / CUDA 13.1 ... Co-Authored-By: Claude Sonnet 4.6 <[email protected]>	2026-06-22 12:02:37 +00:00
osobhandClaude Opus 4.8	96809d48a1	SMT D314 (rustytorch): gradcheck tanh/sigmoid + GatedMemoryUpdater (GRU cell) ... F.1 — finite-difference gradchecks for tanh, sigmoid, and the exact gated composite (1-z)*m + z*c (z=sigmoid, c=tanh) added to tape_cpu_gradcheck.rs. All pass (rel-err < 2e-2) — the activation VJPs that already existed are now proven correct on the real CpuBackend (E0 discipline), so the gated cell can rely on them. F.2 — GatedMemoryUpdater: a GRU-style gated recurrent memory cell. z = sigmoid([M‖x]·W_z); c = tanh([M‖x]·W_c); M_t = (1-z)⊙M + z⊙c The convex update is a non-expansion (|M_t| ≤ max(|M_0|, 1)), so free rollout stays bounded with NO clamp — and the learned gate can both jump at a regime switch (z≈1) and hold+denoise in steady state (z≈0), which the residual+leaky ClonedMemoryUpdater cannot. Same method surface (new/step/predict/train_step/ train_step_memory) so the omni-think facade is cell-generic. Tests: gated cell trains (loss drops); 500-step free rollout stays in [-1,1] without a clamp. clippy(-D)/fmt clean. Co-Authored-By: Claude Opus 4.8 (1M context) <[email protected]>	2026-06-16 21:09:10 -07:00
osobhandClaude Opus 4.8	9a31a07cc9	rtx-autograd: training smoke tests proving the tape learns ... End-to-end training on `Autodiff<CpuBackend>` (forward → backward → extract grads → SGD → repeat), guarding the gradient-correctness fixes: - `mlp_trains_and_loss_decreases`: 2-layer MLP (matmul + gelu), loss 8.65 → 0.39. - `attention_set_encoder_learns_window_mean`: a minimal attention set-encoder (the SMT predictive-state teacher shape) learns to predict its input window's per-dim mean, loss 0.27 → ~0.0. The embedding fans out to Q/K/V and the residual (4 uses), so this also regression-guards the fan-out gradient accumulation fix inside a real attention block. All ops used are gradient-checked in `tape_cpu_gradcheck.rs`. Co-Authored-By: Claude Opus 4.8 (1M context) <[email protected]>	2026-06-15 21:24:56 -07:00
osobhandClaude Opus 4.8	fc895a2de5	rtx-autograd: make the tape correct + sound on real backends ... The decorator autograd (`Autodiff<B>`) had never been gradient-checked against a real tensor backend — the entire test suite runs on a shape-only `MockBackend` whose ops return their input, so they validate graph structure but never gradient values. Running it through `CpuBackend` for the first time (new `tests/tape_cpu_gradcheck.rs`, finite-difference checks) surfaced three bugs that made the tape unusable for training; this fixes all three. 1. Double-free / UB in the dimension-erasure cast. The backward ops cast a tensor to its runtime const-generic dimension via `mem::transmute_copy::<_, TensorPrimitive<N>>(&src)` in ~100 sites. That bit-copies the owned `Vec` without forgetting the source, so two values own one buffer → double-free on any heap-backed backend (and Stacked-Borrows UB from the typed pun). Replaced every site with a single `into_dim` helper that is now **fully safe** — it round-trips through `to_data`/`from_data` and rebuilds the shape with `array::from_fn`, no `unsafe` at all. (This is why the whole repo previously bypassed the tape with analytic backward.) 2. Fan-out gradients were silently dropped. `accumulate_gradients` was a stub that returned one path and discarded the other, and `AutodiffTensor::clone` minted a fresh `TensorId`. Together, reusing a tensor (residuals, `mul(s, s)`, shared Q/K/V — universal in transformers) split its gradient across two ids and summed neither, yielding a fraction of the true value. `accumulate_gradients` now sums via `B::add`; `clone` preserves the id so fan-out paths collide on one sink. 3. Softmax backward panicked. `SoftmaxBackward` / `stable_softmax_backward` subtracted a keep-dim row-sum from the full-shape grad, but the elementwise backends assert equal shapes (no broadcasting). Added `broadcast_along_dim` to tile the row-sum to full width first. Verified: `tape_cpu_gradcheck` (matmul, fan-out add·mul, softmax) passes with rel-err < 2e-2 vs central differences; full `rtx-autograd` suite green (263 passed, 0 failed); lib clippy `-D warnings` clean. Known follow-up (out of scope): `cargo miri test` still aborts on a Stacked-Borrows / integer-to-pointer violation inside `rtx-backend-cpu`'s buffer internals — a grad-free `from_data`+`add`+`sum` probe reproduces the identical error, so it is pre-existing backend UB, not an autograd issue. Co-Authored-By: Claude Opus 4.8 (1M context) <[email protected]>	2026-06-15 21:06:32 -07:00
osobh	5c2ee63d53	GPU Mamba forward + rtx-tensor device-pointer API + matrix exponential ... Persist accumulated WIP across rtx-tensor / rtx-transformers / rtx-runtime. Two related feature groups: GPU enablement (unblocks the Phase-3 spec §8 CUDA Mamba path): - rtx-tensor: `Tensor::cuda_device_ptr()` + storage GPU-buffer accessors (`raw_ptr.rs`) expose the raw CUdeviceptr that kernel launches need — the "rtx-tensor GPU memory access API" the Mamba CUDA kernels were blocked on. - rtx-transformers: `MambaBlock::forward_cuda` runs the four linear projections through cuBLAS on-device (in/out/x/dt_proj), keeping the selective scan + conv1d + activations on CPU; dispatched automatically from `forward` when on a CUDA device under the `cuda` feature. Updated `mamba_cuda_kernels.rs` accordingly. - supporting plumbing in rtx-runtime stream/bridge and rtx-tensor storage/conversion/concatenation/creation + rtx-flash-attention. Linear algebra (rtx-tensor): - `linalg/matrix_exp.rs`: real matrix exponential via scaling-and-squaring with a degree-13 Padé approximant (Higham 2005), f64 internally. - `complex/linalg.rs`: complex matmul/adjoint, Hermitian eigendecomposition (`ComplexEigenResult`), and the complex matrix exponential, nalgebra-backed. - tests for both. Builds verified on the CPU path (`cargo check -p rtx-tensor -p rtx-transformers -p rtx-runtime -p rtx-flash-attention` clean). The `cuda` feature and the rtx-backend-cuda NVCC build remain unbuildable on this host (CUDA/glibc header mismatch) — pre-existing and unrelated to these changes.	2026-06-15 18:51:30 -07:00
Omar SobhandClaude Opus 4.6	0a17f170e6	test(rtx-tensor): add coverage tests for GenericTensor uncovered branches ... Add 10 new tests exercising previously uncovered GenericTensor operations: leaky_relu, elu, gt_scalar, var, var_dim, conv2d (identity kernel, stride, grad propagation), max_pool2d, and avg_pool2d. Also add test_utils.rs module for shared test helpers. SDLC-Coverage: rtx-tensor generic/tensor.rs 19.6% → targeting ~40%+ Co-Authored-By: Claude Opus 4.6 <[email protected]>	2026-05-14 19:25:11 -07:00
redclawsystems	ae53983c03	style: cargo fmt --all (18 files) ... Auto-merged by ci-doctor.	2026-05-07 16:30:04 +00:00
3 people	3e3e8819f6	rtx-tensor + rtx-transformers: deterministic init + Mamba weight persistence ... Two coordinated additions for the omni-cortex D249/D250 work: rtx-tensor: Tensor::randn_seeded(shape, device, seed) — like randn() but routes through StdRng::seed_from_u64(seed) so two calls with (shape, device, seed) produce bit-exact identical tensors. CPU is the canonical generator; GPU calls go via to_device transfer. Required for reproducible model init. rtx-transformers: MambaBlock gains: - new_seeded(config, device, seed) — every internal weight tensor initialised via randn_seeded() with per-tensor SplitMix64-derived seeds. Two calls with the same (config, device, seed) → bit- exact identical block. - persistence_tensors() -> Vec<(&'static str, &Tensor)> — read-only view of the six (or seven, with conv_bias) internal weight tensors with canonical names (in_proj, conv1d_weight, conv1d_bias?, A_log, dt_proj, out_proj). Stable across versions so safetensors round-trip works. - from_persistence_tensors(config, device, HashMap<String, Tensor>) — rebuild a MambaBlock from a name → tensor map. Validates each tensor's shape against the config and surfaces clean errors on mismatch (so wrong-DIM safetensors loads fail explicitly). These three primitives together give omni-cortex's D249 (operator- seeded determinism) and D250 (safetensors round-trip + BLAKE3 hash pin) clean library hooks without exposing MambaBlock's private fields. Co-Authored-By: Claude Opus 4.7 (1M context) <[email protected]>	2026-05-04 05:26:27 -07:00
builderandClaude Sonnet 4.6	301f223b91	refactor(rustytorch): full clean review 2026-04-30 ... - fix(workspace): exclude crates/training/rtx-distributed from workspace members — RNCCL path deps absent in standalone checkout blocked all cargo operations - refactor(rtx-backend-webgpu): split compute.rs (1654 lines) into compute/mod.rs (1040) + compute/conv.rs (628) — both within 1250-line limit - fix(rtx-bench): add missing src/bin/main.rs declared in [[bin]] Cargo.toml entry - fix(gitignore): narrow `bin/` exclusion to /bin/ only; add !**/src/bin/ exception to allow Rust source binary directories - style(rtx-eval): 67x "literal".to_string() → "literal".to_owned() in automation, validation, metrics, lib, core, error modules and build.rs All tests pass (64 tests across rtx-eval + rtx-backend-webgpu, 0 failures). Clippy clean (-D warnings) on all changed crates. Co-Authored-By: Claude Sonnet 4.6 <[email protected]>	2026-04-30 08:27:50 -07:00
Omar Sobh	6a03aeba61	fix(cuda+csm): P0 rtx-backend-cuda compile fix + P2 rtx-csm clippy cleanup (#9) ... Co-authored-by: Omar Sobh <[email protected]> Co-committed-by: Omar Sobh <[email protected]>	2026-04-30 05:24:58 +00:00
osobhandClaude Opus 4.7	6d59251c51	rtx-nn / rtx-multimodal: cargo fmt reformatting ... Pure formatting changes across rtx-nn (conv_transpose1d, conv/mod, rnn/lstm) and rtx-multimodal (audio/generation, audio/source_separation): multi-line braces, trailing commas, import ordering. No logic changes. Co-Authored-By: Claude Opus 4.7 (1M context) <[email protected]>	2026-04-27 18:37:07 -07:00
redclawsystems	593b32f940	Merge branch 'main' into rust-thiserror-v2-upgrade	2026-04-27 10:51:49 +00:00
redclawsystems	bdef2b746a	Merge pull request 'Rust Scan 2026-04-25: rustytorch' (#1) from rust-improvement/scan-20260425-222549 into main ... Reviewed-on: #1	2026-04-27 10:51:26 +00:00
Omar Sobh	16161bb9df	deps: align all 56 per-crate Cargo.toml files to thiserror v2 ... The workspace root was upgraded to thiserror = "2" in an earlier commit, but 56 per-crate Cargo.toml files still independently declared "1.0". These crates do not use workspace.dependencies inheritance for thiserror. All updated to thiserror = "2" for complete fleet alignment. Includes: rtx-backend, rtx-tensor, rtx-losses, rtx-backend-cuda/rocm/metal, all training crates (rtx-auto, rtx-rl, rtx-distributed, rtx-federated, etc.), specialized crates (rtx-science, rtx-platform, rtx-nmf, rtx-neuro-*), production crates (rtx-streaming, rtx-serving-api), and all demo crates. cargo check --workspace: PASSES.	2026-04-26 11:45:14 -07:00
Omar Sobh	a88d254518	rust-scan: edition 2024 clippy clean, workspace lint fixes 2026-04-25	2026-04-25 22:25:49 -07:00
osobhandClaude Opus 4.7	15b62a8f6e	rtx-interpret: fix decoder transpose in SAE compute_and_apply_gradients ... The encoder-gradient path through the decoder was transposing the decoder before the matmul, producing `[batch, d_model] × [d_sae, d_model]` — a shape mismatch for every batch > 1. The decoder is stored as `[d_model, d_sae]`, so `recon_grad @ decoder` is already the right shape (and matches the comment at the call site, which reads "recon_grad @ decoder @ d_relu"). All 9 existing `sae::tests` still pass. Omni-Cortex's `LatentDictionary` now trains correctly on batches larger than 1. Co-Authored-By: Claude Opus 4.7 (1M context) <[email protected]>	2026-04-24 13:58:44 -07:00
osobhandClaude Opus 4.6	85b77d49f2	Add audio neural layers and model architectures for ClawSample integration ... New nn layers: - ConvTranspose1d with stride, padding, output_padding (9 tests) - LSTM/BiLSTM with multi-layer support and hidden state (10 tests) Audio source separation: - Demucs ONNX inference with segmented overlap-add processing - Native HtDemucs architecture (encoder/decoder with BiLSTM bottleneck) - StemType enum: vocals, drums, bass, other, piano, guitar Audio generation: - Stable Audio Open ONNX inference scaffold - GenerationParams (prompt, duration, steps, cfg_scale, seed) ONNX export scripts: - export_demucs_onnx.py — Demucs v4 to ONNX with segment chunking - export_stable_audio_onnx.py — Stable Audio Open components - export_mert_onnx.py — MERT music understanding transformer Co-Authored-By: Claude Opus 4.6 (1M context) <[email protected]>	2026-04-17 12:27:12 -07:00