PERF-2 P3: the batched device V-cycle microbenchmark — mg_vcycle.cu (masked variable-coefficient five-point red-black half-sweeps, residual, CSR restriction in a fixed order, prolongation, coarsest sweeps; [K][n] layout, blockIdx.y = march), LevelExport/export_hierarchy and vcycle_f32_reference on the CPU side, and the ignored cuda-feature test that checks the K = 1 device V-cycle against the CPU f32 reference and times K = 1 / 8 / 16 per march

Co-Authored-By: Claude Fable 5.1 <[email protected]>
Claude-Session: https://claude.ai/code/session_01YJPeT6WA2e7YvAnS875AHL

crates/specialized/rtx-cfd/src/kernels/cuda/mg_vcycle.cu

@@ -0,0 +1,107 @@
+/**
+ * PERF-2 P3 (`docs/perf2_campaign.md`): the multigrid V-cycle's maps for a
+ * MASKED, VARIABLE-COEFFICIENT five-point operator, batched over K marches.
+ * Layout: every per-cell array is [K][n] (march-major, n = nx*ny of the
+ * level); the index lists (cells, colours, children) are shared across the
+ * batch in this benchmark. blockIdx.y = the march.
+ */
+extern "C" __global__ void mg_rb_half(
+    int n_col, const unsigned int* __restrict__ col, int n,
+    const float* __restrict__ ae, const float* __restrict__ aw,
+    const float* __restrict__ an, const float* __restrict__ as_,
+    const float* __restrict__ ap, const float* __restrict__ b,
+    float* __restrict__ x, int nx)
+{
+    int t = blockIdx.x * blockDim.x + threadIdx.x;
+    if (t >= n_col) return;
+    int base = blockIdx.y * n;
+    int idx = col[t];
+    int g = base + idx;
+    float s = 0.0f;
+    float e = ae[g]; if (e != 0.0f) s += e * x[g + 1];
+    float w = aw[g]; if (w != 0.0f) s += w * x[g - 1];
+    float nn = an[g]; if (nn != 0.0f) s += nn * x[g + nx];
+    float ss = as_[g]; if (ss != 0.0f) s += ss * x[g - nx];
+    x[g] = (b[g] + s) / ap[g];
+}
+
+extern "C" __global__ void mg_residual(
+    int n_cells, const unsigned int* __restrict__ cells, int n,
+    const float* __restrict__ ae, const float* __restrict__ aw,
+    const float* __restrict__ an, const float* __restrict__ as_,
+    const float* __restrict__ ap, const float* __restrict__ b,
+    const float* __restrict__ x, float* __restrict__ r, int nx)
+{
+    int t = blockIdx.x * blockDim.x + threadIdx.x;
+    if (t >= n_cells) return;
+    int base = blockIdx.y * n;
+    int g = base + cells[t];
+    float s = 0.0f;
+    float e = ae[g]; if (e != 0.0f) s += e * x[g + 1];
+    float w = aw[g]; if (w != 0.0f) s += w * x[g - 1];
+    float nn = an[g]; if (nn != 0.0f) s += nn * x[g + nx];
+    float ss = as_[g]; if (ss != 0.0f) s += ss * x[g - nx];
+    r[g] = b[g] - (ap[g] * x[g] - s);
+}
+
+/* b_c[c] = sum of r_f over the children of coarse cell c (fixed order). */
+extern "C" __global__ void mg_restrict(
+    int n_coarse, const unsigned int* __restrict__ coarse_cells,
+    const unsigned int* __restrict__ children_ptr, const unsigned int* __restrict__ children_idx,
+    int n_f, int n_c, const float* __restrict__ r_f, float* __restrict__ b_c)
+{
+    int t = blockIdx.x * blockDim.x + threadIdx.x;
+    if (t >= n_coarse) return;
+    int k = blockIdx.y;
+    const float* rf = r_f + (size_t)k * n_f;
+    float s = 0.0f;
+    for (unsigned int p = children_ptr[t]; p < children_ptr[t + 1]; ++p) s += rf[children_idx[p]];
+    b_c[(size_t)k * n_c + coarse_cells[t]] = s;
+}
+
+/* x_f += 2 x_c[coarse_of[idx]] */
+extern "C" __global__ void mg_prolong(
+    int n_cells, const unsigned int* __restrict__ cells, const unsigned int* __restrict__ coarse_of,
+    int n_f, int n_c, float* __restrict__ x_f, const float* __restrict__ x_c)
+{
+    int t = blockIdx.x * blockDim.x + threadIdx.x;
+    if (t >= n_cells) return;
+    int k = blockIdx.y;
+    int idx = cells[t];
+    x_f[(size_t)k * n_f + idx] += 2.0f * x_c[(size_t)k * n_c + coarse_of[idx]];
+}
+
+extern "C" __global__ void mg_zero(int n_cells, const unsigned int* __restrict__ cells, int n, float* __restrict__ x)
+{
+    int t = blockIdx.x * blockDim.x + threadIdx.x;
+    if (t >= n_cells) return;
+    x[(size_t)blockIdx.y * n + cells[t]] = 0.0f;
+}
+
+/* The coarsest level: one thread per march, `sweeps` symmetric lexicographic sweeps over <= a few dozen cells. */
+extern "C" __global__ void mg_coarsest(
+    int K, int n_cells, const unsigned int* __restrict__ cells, int n,
+    const float* __restrict__ ae, const float* __restrict__ aw,
+    const float* __restrict__ an, const float* __restrict__ as_,
+    const float* __restrict__ ap, const float* __restrict__ b,
+    float* __restrict__ x, int nx, int sweeps)
+{
+    int k = blockIdx.x * blockDim.x + threadIdx.x;
+    if (k >= K) return;
+    int base = k * n;
+    for (int t = 0; t < n_cells; ++t) x[base + cells[t]] = 0.0f;
+    for (int sw = 0; sw < sweeps; ++sw) {
+        for (int pass = 0; pass < 2; ++pass) {
+            for (int q = 0; q < n_cells; ++q) {
+                int t = pass == 0 ? q : n_cells - 1 - q;
+                int g = base + cells[t];
+                float s = 0.0f;
+                float e = ae[g]; if (e != 0.0f) s += e * x[g + 1];
+                float w = aw[g]; if (w != 0.0f) s += w * x[g - 1];
+                float nn = an[g]; if (nn != 0.0f) s += nn * x[g + nx];
+                float ss = as_[g]; if (ss != 0.0f) s += ss * x[g - nx];
+                x[g] = (b[g] + s) / ap[g];
+            }
+        }
+    }
+}

crates/specialized/rtx-cfd/src/solvers/incompressible/mod.rs

@@ -65,7 +65,8 @@ pub use piso::{PisoParameters, PisoResult, PisoSolver};
 #[cfg(feature = "cuda")]
 pub use piso_gpu::PisoGpuSolver;
 pub use poisson::{
-    MgPrecision, MgSmoother, MultigridParameters, PcgCache, PoissonProblem, PoissonSolution,
+    LevelExport, MgPrecision, MgSmoother, MultigridParameters, PcgCache, PoissonProblem,
+    PoissonSolution, export_hierarchy, vcycle_f32_reference,
     PoissonSolverKind, configure_threads, solve_multigrid_pcg, solve_multigrid_pcg_cached,
 };
 pub use polygon_sdf::PolygonSdf;

crates/specialized/rtx-cfd/src/solvers/incompressible/poisson.rs

@@ -1001,6 +1001,99 @@ pub fn configure_threads(threads: usize) -> usize {
     n
 }
 
+/// PERF-2 P3 (`docs/perf2_campaign.md`): one hierarchy level exported for a
+/// device V-cycle — the sanitised f32 coefficients, the active-cell and
+/// colour index lists, the parent map, and the coarse cells' children in
+/// CSR form (so a restriction can sum in a fixed order on the device).
+#[derive(Debug, Clone)]
+pub struct LevelExport {
+    pub nx: usize,
+    pub ny: usize,
+    pub cells: Vec<u32>,
+    pub red: Vec<u32>,
+    pub black: Vec<u32>,
+    /// Fine cell → coarse cell (`u32::MAX` without an equation; empty on
+    /// the coarsest level).
+    pub coarse_of: Vec<u32>,
+    /// For the NEXT level's cells, in its `cells` order: the fine cells
+    /// restricting into each (CSR: `children_ptr[c]..children_ptr[c + 1]`).
+    pub children_ptr: Vec<u32>,
+    pub children_idx: Vec<u32>,
+    pub ae: Vec<f32>,
+    pub aw: Vec<f32>,
+    pub an: Vec<f32>,
+    pub as_: Vec<f32>,
+    pub ap: Vec<f32>,
+}
+
+/// The f32 hierarchy of `problem` (red-black colour lists included), level
+/// 0 fine, for a device implementation of [`Hierarchy::apply_preconditioner`].
+pub fn export_hierarchy(problem: &PoissonProblem, params: &MultigridParameters) -> Vec<LevelExport> {
+    let hier = Hierarchy::<f32>::build(problem, params);
+    let depth = hier.levels.len();
+    (0..depth)
+        .map(|l| {
+            let lv = &hier.levels[l];
+            let to_u32 = |v: &[usize]| v.iter().map(|&i| i as u32).collect::<Vec<u32>>();
+            let (children_ptr, children_idx) = if l + 1 < depth {
+                let coarse = &hier.levels[l + 1];
+                let mut pos = vec![usize::MAX; coarse.problem.nx * coarse.problem.ny];
+                for (k, &c) in coarse.cells.iter().enumerate() {
+                    pos[c] = k;
+                }
+                let mut lists: Vec<Vec<u32>> = vec![Vec::new(); coarse.cells.len()];
+                for &idx in &lv.cells {
+                    let c = lv.coarse_of[idx];
+                    if coarse.active[c] {
+                        lists[pos[c]].push(idx as u32);
+                    }
+                }
+                let mut ptr = Vec::with_capacity(lists.len() + 1);
+                let mut flat = Vec::new();
+                ptr.push(0u32);
+                for list in &lists {
+                    flat.extend_from_slice(list);
+                    ptr.push(flat.len() as u32);
+                }
+                (ptr, flat)
+            } else {
+                (Vec::new(), Vec::new())
+            };
+            LevelExport {
+                nx: lv.problem.nx,
+                ny: lv.problem.ny,
+                cells: to_u32(&lv.cells),
+                red: to_u32(&lv.red),
+                black: to_u32(&lv.black),
+                coarse_of: lv
+                    .coarse_of
+                    .iter()
+                    .map(|&c| if c == usize::MAX { u32::MAX } else { c as u32 })
+                    .collect(),
+                children_ptr,
+                children_idx,
+                ae: lv.ae.clone(),
+                aw: lv.aw.clone(),
+                an: lv.an.clone(),
+                as_: lv.as_.clone(),
+                ap: lv.ap.clone(),
+            }
+        })
+        .collect()
+}
+
+/// One f32 V-cycle of `problem`'s hierarchy on `r` (the CPU reference for a
+/// device V-cycle): `z = M⁻¹ r` exactly as the preconditioner computes it.
+pub fn vcycle_f32_reference(
+    problem: &PoissonProblem,
+    params: &MultigridParameters,
+    r: &[f64],
+    z: &mut [f64],
+) {
+    let mut hier = Hierarchy::<f32>::build(problem, params);
+    hier.apply_preconditioner(r, z);
+}
+
 /// A reusable prepared solver per V-cycle precision (PERF-2 P1.1): the
 /// operator's hierarchy is rebuilt only when the operator changes.
 #[derive(Default)]