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osobhandClaude Opus 5 97e65f2adf feat(accel): runtime-dispatched int8 dot product

The int8-quantised HNSW index compared vectors with a scalar loop that
the compiler vectorised for the x86-64 baseline (SSE2), while the f32
path it was measured against goes through `clawhdf5-accel` and runs
AVX2. So the ~13% throughput cost recorded for `quantized_index` was a
missing kernel rather than a property of int8.

`clawhdf5_accel::dot_i8` adds a scalar fallback and an AVX2 path:
sign-extend each 16-byte half to i16, then `madd_epi16`, which
multiplies and sums adjacent pairs straight into i32 lanes. It is
dispatched through the same detected backend as the f32 kernels, and
the index now calls it.

Integer arithmetic, so the SIMD path must agree with scalar bit for
bit — tested at lengths that are and are not multiples of the block,
and at the -128 extreme for overflow.

Co-Authored-By: Claude Opus 5 (1M context) <[email protected]>

2026-09-20 17:30:56 -07:00

src

feat(accel): runtime-dispatched int8 dot product

2026-09-20 17:30:56 -07:00

Cargo.toml

chore(release): v2.6.0

2026-09-20 06:01:31 -07:00

README.md

docs: fix stale package names, counts, and CLI subcommands

2026-06-03 11:17:04 +00:00

README.md

clawhdf5-accel

SIMD-accelerated operations for clawhdf5.

Features

AVX2 and NEON SIMD acceleration
AVX-512 support (avx512 feature)
Float16 conversion (float16 feature)
CRC32 checksum acceleration

Usage

use clawhdf5_accel::checksum::crc32_simd;

let crc = crc32_simd(&data);

License

MIT