feat(accel): runtime-dispatched int8 dot product
The int8-quantised HNSW index compared vectors with a scalar loop that the compiler vectorised for the x86-64 baseline (SSE2), while the f32 path it was measured against goes through `clawhdf5-accel` and runs AVX2. So the ~13% throughput cost recorded for `quantized_index` was a missing kernel rather than a property of int8. `clawhdf5_accel::dot_i8` adds a scalar fallback and an AVX2 path: sign-extend each 16-byte half to i16, then `madd_epi16`, which multiplies and sums adjacent pairs straight into i32 lanes. It is dispatched through the same detected backend as the f32 kernels, and the index now calls it. Integer arithmetic, so the SIMD path must agree with scalar bit for bit — tested at lengths that are and are not multiples of the block, and at the -128 extreme for overflow. Co-Authored-By: Claude Opus 5 (1M context) <[email protected]>
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@@ -140,3 +140,33 @@ fn f16_to_f32_soft(h: u16) -> f32 {
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f32::from_bits(f32_bits)
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}
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/// Dot product of two `i8` slices, widened to `i32`.
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///
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/// `dim` terms of at most `127 * 127` fit an `i32` for any realistic
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/// dimension (over 130 000 terms before overflow is possible).
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pub fn dot_i8(a: &[i8], b: &[i8]) -> i32 {
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assert_eq!(a.len(), b.len());
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// Four independent accumulators over 32-lane blocks: the widening product
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// has to sit in a fixed-length chunk for the vectoriser to see it, and the
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// separate accumulators keep it off one dependency chain.
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const LANE: usize = 8;
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let (a_blocks, a_tail) = a.as_chunks::<{ LANE * 4 }>();
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let (b_blocks, b_tail) = b.as_chunks::<{ LANE * 4 }>();
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let mut acc = [0i32; 4];
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for (x, y) in a_blocks.iter().zip(b_blocks) {
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for (lane, slot) in acc.iter_mut().enumerate() {
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let mut sum = 0i32;
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for k in 0..LANE {
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sum += i32::from(x[lane * LANE + k]) * i32::from(y[lane * LANE + k]);
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}
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*slot += sum;
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}
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}
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let tail: i32 = a_tail
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.iter()
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.zip(b_tail)
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.map(|(&x, &y)| i32::from(x) * i32::from(y))
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.sum();
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acc[0] + acc[1] + acc[2] + acc[3] + tail
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}
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